Language Breakdown
Lines of code distribution across 7 owned repositories
1.2M
Total LOC
Verilog
1,077,558 lines
93.0%
N/A
Tcl
35,571 lines
3.1%
N/A
Jupyter Notebook
12,955 lines
1.1%
N/A
CSS
11,866 lines
1.0%
N/A
HTML
9,502 lines
0.8%
N/A
Other
10,761 lines
0.9%
N/A
I
I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
Verilog
Tcl
Jupyter Notebook
CSS
HTML
Collaboration Network
Global Impact visualization
Repos
7
PRs
0
Growth
+18%
Top Collaborators
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Coding Streak
Contribution activity over the past year
2 days
14
Contributions
8
Commits
0
Pull Requests
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Followers
1
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Top Repositories
Praktikum_VLSI
0
0
Gnuplot
VLSI_4Bit_Shift_Register
0
0
Verilog
VLSI_4Bit_Down_Counter
0
0
Batchfile
VLSI_IC_Design_Projects
0
0
VLSI_Inverter_Design
This project implements the design of a CMOS inverter using open-source EDA tools, OpenLane, and the SkyWater 130 nm PDK.
0
0
Verilog
Emotion-Detection
0
0
Jupyter Notebook
Kendali-RistTIE-2025
0
0
CSS
Open Source Impact
Contributions to external projects
0 merged PRs
No external contributions found.